A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET

This paper details the implementation of a highly pipelined 2.5 Gbps Point-to-Point-Protocol Packet Processor (P) aimed for the latest System-on-a-Programmable-Chip (SoPC) technology. Throughput rates beyond 2.5 Gbps based on FPGA technology could be achieved by designing a new highly pipelined and parallel processing architecture for frames and datagrams. A novel pipelined data sorting mechanism with an extremely low resynchronization buffer and backpressure scheme are introduced to keep the data memory requirements as low as possible for embedded on-chip applications.